v320usc high integration, low cost pci system controller for 32 bit mips? and superh? processors t glueless interf ace betw een the popular mips? and superh? processors and the industr y standard pci bus t fully compliant with pci 2.2 specification t configur ab le f or pr imar y master , b us master , and target pci oper ation t sdram controller with suppor t f or enhanced sdram t up to 1kb yte b urst access to (e)sdram from pci, 32b yte from the local processor t 640 b ytes of on chip fifo stor age with d ynamic band width alloca tion? t on-the-fly b yte order (endian) con v ersion t i 2 o-ready? a tu and messaging unit t prog r ammab le chip select/per ipher al de vice strobe gener ation t picmg hot sw ap ready including on-chip bias v oltage t 3.3v oper ation with 5v toler ant i/o t 208-pin pqfp pac kage t up to 75mhz local b us cloc k with separ ate asynchronous pci cloc k up to 33mhz t 2-32 bit timers , w atchdog, hear tbeat and b us w atch timers t initialization through local processor , pci, or ser ial eepr om the v320usc is a 3 r d generation pci pr oduct that also integrates many of the functions that ar e needed in typical embedded systems. its high level of integration r esults in a ver y high per for mance, low cost system solution for some of the most popular 32/64 bit pr ocessors available. 3 way architecture a 3-bus ar chitectur e is employed by the v320usc so that the pr ocessor , pci bus and memor y system can all operate independently when a mips pr ocessor is used. as a r esult, the usc is r eally 3 bridges in one package. w ith 3 concur r ent buses, system per for mance is incr eased and deadlock conditions eliminated. pci controller and more the pci bus is an impor tant standar d used in today's embedded systems. while the v320usc addr esses this impor tant r equir ement, it is also far mor e than a pci inter face. it also contr ols the most essential components of an embedded system such as sdram memor y , flash memor y and peripherals using a ver y flexible memor y contr oller and peripheral contr ol unit. direct processor interface some of the most popular and cost ef fective pr ocessors in the industr y , such as mips and superh, will connect dir ectly to the v320usc. the inter faces ar e designed to pr ovide low latency of access by employing lar ge on-chip buf fers that utilize the dynamic bandwidth allocation? featur e. this featur e allows the on-chip buf fers to be mor e fully utilized. industrial strength pci compactpci applications will benefit fr om the hot swap featur es implemented by the v320usc accor ding to the picmg? specification. the v320usc is a "hot swap ready" silicon device as defined by the specification. for this, the v320usc employs custom designed pci buf fers that pr ovide the necessar y bias voltage. this eliminates the need for mor e than 40 exter nal components that would be r equir ed by other solutions. when the bias voltage is enabled, the input buf fers ar e automatically disabled to pr event excessive cur r ent flow thr ough the p and n devices of the input buf fers. other picmg r equir ements for hot swap such as the ejector input, extended configuration registers (hs_csr, and ecp), blue led and enum# output ar e pr ovided. v3 has long established itself as a leader in industrial applications with all components in the pr oduct line, including the v320usc, available as industrial temperatur e devices.
cost effective solutions that simplify embedded system design! mastering the pci bus it would be pointless to emphasize the 132mb/s peak pci transfer rate of the v320usc (which is at the theor etical maximum). thr oughput in r eal world applications is what counts and that is exactly what the v320usc was designed to do. t o achieve this, long sustained bursting is the key . the pci bus master inter face on the v320usc guarantees the highest possible overall bus utilization by employing lar ge on chip buf fers and never inser ting wait states. the lar ge on chip memor y (640 bytes total) ensur es long bursts so that the over head of star ting a cycle ar e amor tized over mor e data. when the usc can no longer handle mor e data then it will end the transfer , rather than inser t irdy wait states, so that other masters can utilize the bus. pci target applications the v320usc pr ovides 5 independent slave inter faces: 1-inter nal r egister access, 2-sdram memor y aper tur es (one of which also acts as an i 2 o a tu), a peripheral aper tur e and a rom aper tur e. except for the inter nal r egister aper tur e, all other slave aper tur es ar e dir ected thr ough fifo buf fers that ar e designed to maximize bus utilization. when the v320usc, as a tar get, is accessed by a pci master , it will either r etur n a tar get r eady one cycle after frame or it will issue a r etr y . a r etr y will be issued if the write fifo is full (writes) or ther e is no pr efetched r ead data (r eads). this allows other pci transactions to pr oceed and keep the bus occupied. when the v320usc is r eady to deliver data then it will asser t trdy and keep it asser ted as long as data can move. when data cannot move, the usc will ter minate the transfer with the last data rather than inser t tar get wait states. dual dma engine with descriptor processing t wo fully independent dma engines pr ovide one of the fastest methods of moving data in the system. each engine is capable of pr ocessing descriptors in either pci space or local memor y . the unique pooled buf fer? ar chitectur e of the v320usc guarantees high bus utilization and long sustained bursts. t wo fifo buf fers (128 bytes total) ar e dedicated to the dma engines. the buf fers can be dynamically allocated to the dma engines on a priority basis. when a single or high priority dma engine is activated, then both buf fers can be allocated to it to allow longer bursts. burst length, however , is not limited to total buf fer size since simultaneous fill and drain can easily be achieved. when both dma engines ar e activated together , then they can be prioritized to allow fair and equal access to the buf fers, first-come first-ser ve or fixed priority . other dma featur es t anywher e-to-anywher e dma: pci, sdram or peripheral to pci, sdram or peripheral t descriptor based scatter/gather capability t descriptor write-back to indicate completion of an individual descriptor link and to allow looped descriptors t block fill t inter r upt on end of t ransfer (eot) or end of link (eol) t pr ogrammable byte lane swapping t burst loading of descriptors p ci mast er l oc al t o pci t r ans f er dma engine t r ans f er w rite fif o read fif o (2) dma engines (2) p ci t ar get in ternal regis ter a cc ess memory/ p eripher al int erfac e int ernal regist er s memory aper tur e l ocal p r oc essor int erfac e w rite fif o read pipeline l oc al t o pci aper tur e 1 l oc al t o pci aper tur e 0 i 2 o mesage unit rom aper tur e memory or i 2 o aper tur e p eripher al aper tur e w rite fif o read fif o 128 byte buf f er p ool rom aper tur e in ternal regis ter a cc ess p eripher al aper tur e memory aper tur e sdram con tr oller p eripher al con tr oller serial eep rom timer s (5) p ci bus mip s p r oc essor bus in terrup t con tr oller (4) ho t sw ap con tr oller memory/p eripher al bus p ci mast er l oc al t o pci t r ans f er dma engine t r ans f er w rite fif o read fif o (2) dma engines (2) p ci t ar get in ternal regis ter a cc ess int ernal p eripher als int ernal regist er s memory aper tur e l ocal t ar get int erfac e l oc al t o pci aper tur e 1 l oc al t o pci aper tur e 0 i 2 o message unit rom aper tur e memory or i 2 o aper tur e p eripher al aper tur e 128 byte buf f er p ool in ternal regis ter a cc ess serial eep rom timer s (4) p ci bus superh p r oc essor bus in terrup t con tr oller (4) ho t sw ap con tr oller l ocal mast er int erfac e sdram con tr oller p eripher al con tr oller w rite fif o read fif o figure 2. v320usc bloc k dia gram (superh mode) figure 1. v320usc bloc k dia gram (mips mode)
tuning for performance the dynamic bandwidth allocation ar chitectur e allows the application developer to fine tune the 640 bytes of on-chip buf fers to achieve the best overall system per for mance for a specific application. it also allows data to be packed into the on-chip buf fers so that higher utilization is achieved. for example, when the local pr ocessor writes data to the pci, multiple sequential or non-sequential bursts or single cycles can be queued into the posting fifo. fur ther mor e, sequential bursts or single cycles fr om the pr ocessor can be automatically combined into lar ger bursts on the pci bus. these ar e some of the examples of tunable featur es within the v320usc: t the write posting drain strategy can be pr ogrammed to deter mine how aggr essively the local pr ocessor to pci writes will be drained. simultaneous filling and draining allows long bursts to be sustained - even longer than the write-posting buf fer size. t pr efetched r ead data can be stor ed in either a single buf fer or two buf fers (64 bytes total) managed as a least r ecently used cache. w ith dual buf fers, two sequential str eams of data can be pr efetched continuously without scrapping data. t thr esholds for the pr efetch buf fers ar e pr ogrammable to deter mine how aggr essively they will be filled. messaging unit t 32 byte bi-dir ectional mailbox with inter r upts t queue based i 2 o messaging unit (can also be used as a general purpose messaging unit) dual ported sdram interface memor y is at the hear t of most embedded systems and is a key factor in deter mining overall system per for mance. v3 semiconductor was the first company to pr ovide single chip dram contr ol solutions fine-tuned to the appetites of embedded risc pr ocessors. the v320usc builds on that experience by tightly integrating sdram contr ol functions into the pci and pr ocessor inter faces. the r esult is a ver y low latency memor y system that actually behaves like two memor y contr ollers: one optimized for pci access and another optimized for the local pr ocessor . when a mips pr ocessor is used, the sdram contr oller uses a toggle burst or der the same as the pr ocessor . however , for pci access, linear bursts ar e used to pr ovide the gr eatest pci compatibility . when a superh pr ocessor is used, it can access sdram dir ectly and bypass the v320usc. other sdram featur es: t up to 1gb of sdram in 4 blocks t v er y flexible addr ess multiplexing modes (mor e than 100 modes) t fine grained contr ol over sdram timing parameters t i 2 c inter face for r eading configuration data fr om dimms t suppor ts enhanced sdram for higher per for mance t sdram can be accessed by an alter nate bus master peripheral control unit a peripheral contr ol unit (pcu) pr ovides a simple way to inter face 8/16 or 32 bit peripherals to either pci bus or the local pr ocessor . a total of 5 chip select str obes can be generated, each with separately contr olled r ead/write timing characteristics and data width. integrated peripherals as a system contr oller , the v320usc pr ovides additional peripheral functions that ar e r equir ed in a typical embedded system. t 2 - 32 bit general purpose timers can be individually configur ed as a pulse width modulator , rate generator , pulse counter or har dwar e/softwar e trigger ed pulse generator . t w atchdog timer for graceful r ecover y fr om catastr ophic pr ogram failur es t hear tbeat inter r upt timer for r tos inter r upt generation t bus watch timer to pr event system hangs during accesses to un-decoded r egions t 4 channel inter r upt contr oller to generate either pci or local cpu inter r upts and inter r upt cr oss-r outing applications for the v320usc the v320usc is well suited to the most demanding embedded applications in networking, telecom, ser vers, digital video and industrial contr ol. w indows ce developers will benefit fr om the rich featur e set of the v320usc for use in compactpci or set-top box applications. add-in card applications either compactpci, pmc or standar d pci plug-in adapters ar e easily and quickly designed using the v320usc. t ypical applications include xdsl/isdn modems, raid contr ollers and a tm adapters. the usc employs the latest standar ds in power management and intelligent i/o so that the need for pr oprietar y solutions is avoided. the hur ricane evaluation boar d (figur e 3) and accompanying softwar e pr ovides an ideal star ting point to launch your design. figure 3. hurricane ev aluation boar d
host controller application in embedded applications the v320usc makes an ideal host bridge. in this type of application, the usc performs as the main system master. in this capacity, the local processor is responsible for enumerating devices on the pci bus via the usc using either type 0 or type 1 configuration cycles. an example of this application is a set-top box (figure 5). in this application, the operating system and user interface is run on the local processor. peripherals such as graphics controllers and mpeg decoders typically use pci bus as their main interface. the dual ported sdram interface can be used to provide a unified memory for the operating system and the video/graphics sub-systems. with the v320usc acting as the main "hub" of the system, very low component count and system cost is achieved without sacrificing performance. software and design support our goal is to help developers to get their product to market quickly. software tools, reference designs and evaluation boards are available to accelerate development so that the application developer can concentrate on other areas of the design task that help differentiate their product. multiple reference designs are available for the usc and include orcad schematics, printed circuit artwork, windows based configuration tools with source code, local processor initialization source code and user documentation. technical support is available via email, fax and phone. sdram pci bus v320usc superh processor sdram rom i/o devices local bus serial eeprom network, telecom or storage controllers figure 4. plug-in card application sdram pci bus v320usc mips processor sdram rom uart memory bus video graphics controller mpeg decoder 1394 controller cost effective solutions that simplify embedded system design! v3 semiconductor 2348g walsh ave. santa clara, ca 95051 phone: (408)988-1050 fax: (408)988-2601 toll free: (800)488-8410 (canada and us) www.vcubed.com / or www.v3semiconductor.com ?1999 v3 semiconductor corp. is a registered trademark of v3 semiconductor. any other names mentioned herein are the property of their respective owners. v3 semiconductor retains the right to make changes to either the documentation, specification or component without notice. figure 5. embedded host application figure 6. monsoon compactpci board tm usc0000 for more information on the v320usc or other v3 products, please contact:
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